The present invention relates to integrated circuits, and more particularly to integrated circuits having serial interface circuits therein.
FIG. 1 is a schematic block diagram of an integrated circuit containing a digital signal processor (DSP) 100, a serial interface circuit 200 and a coder-decoder circuit (CODEC) 300. The DSP 100 is connected through data and control buses 120 and 130 to the serial interface circuit 200. Although not illustrated in FIG. 1, the DSP 100 may also be associated with various other units which are communicatively coupled to the serial interface circuit 200. A selector 110 is used to select one of the various units associated with the DSP 100 in accordance with a plurality of select signals from the DSP 100. The selector 110 supplies a data output enable signal wr_txd and a data input enable signal rd_rxd through the control bus 120 to the serial interface circuit 200. The serial interface circuit 200 may receive serial data DRX from the CODEC 300 and then convert the received serial data DRX into parallel data which can be transferred to the DSP 100 in response to a frame synchronization signal Fsync and a shift clock signal Sftclk. The serial interface circuit 200 also receives parallel data from the DSP 100 (via the data bus 130), converts the received parallel data into serial data DTX capable of being transferred to the CODEC 300, and transfers the parallel data thus converted to the CODEC 300. A detailed block diagram of the serial interface circuit 200 according to the prior art is illustrated in FIG. 2.
As shown in FIG. 2, the serial interface circuit 200 consists of a first shift register 210, a first data register 220, a second data register 230, a second shift register 240 and a controller 250. The first shift register 210 receives serial data DRX transferred from the CODEC 300 and shifts in the received serial data DRX in response to the shift clock signal Sftclk. The first data register 220 fetches the contents in the corresponding shift register 210 is parallel (in response to a first data register control signal ldrd issued from the controller 250), when the transfer of the serial data DRX from the CODEC 300 has been completed. The first data register 220 then outputs the fetched data through the data bus 130 to the DSP 100 in response to the data input enable signal rd_rxd which is supplied by the selector 110 (via the control bus 120). According to the above-mentioned functional description, the first shift register 210 may be configured as a serial-in-parallel-out (SIPO) buffer register and the first data register 220 may be configured as a parallel-in-parallel-out (PIPO) buffer register.
The second data register 230 receives parallel data to be transferred to the CODEC 300 in response to the data output enable signal wr_txd (which is supplied from the selector 110 through the control bus 120). The received parallel data is then transferred in parallel to the second shift register 240, in response to a second data register control signal Idts from the controller 250. The second shift register 240 shifts out the received parallel data one bit at-a-time in response to each cycle of the shift clock signal Sftclk. The data DTX output from the second shift register 240 is then serially transferred to the CODEC 300. According to above-mentioned functional description, the second shift register 240 may be configured as a parallel-in-serial-out (PISO) buffer register and the second data register 230 may comprise the same PIPO buffer register as the first data register 220.
The controller 250 generates an interrupt signal CINT in response to the shift clock signal Sftclk, the frame synchronization signal Fsync (indicating the end of a frame of the serial data DRX) and a clock signal CLK used in the DSP 100. The interrupt signal CINT is supplied via the control bus 120 to the DSP 100. The interrupt signal CINT causes the selector 110 to generate the data input enable signal rd_rxd (so that the contents of the first data register 220 can be transformed via the data bus 130 to the DSP 100). The data output enable signal wr_txd is also generated by the selector 110 so that parallel data from the DSP 100 can be transferred via the data bus 130 to the serial interface circuit 200.
Unfortunately, the number of bits to be converted by the serial interface circuit 200 cannot be increased without a concomitant increase in the size of the shift and data registers therein. Accordingly, the circuit of FIGS. 1-2 may not be suitable for applications requiring wide bandwidth data transfers.
It is therefore an object of the present invention to provide improved serial interface circuits and methods of operating same.
It is another object of the present invention to provide serial interface circuits having wide bandwidth data transfer capability and methods of operating same.
These and other objects, advantages and features of the present invention are provided by serial interface circuits which comprise first and second data registers responsive to first and second register control signals, respectively, and a shift register responsive to a shift clock signal. The preferred shift register has a serial input port, a serial output port and a parallel input/output port electrically coupled to the first and second data registers. A preferred controller circuit is also provided. This controller circuit, which is responsive to a frame synchronization signal, generates the first and second register control signals during nonoverlapping time intervals to thereby enable use of only one shift register by preventing interference between data being transferred to and from the first and second data registers, respectively. According to preferred aspects of the present invention, the frame synchronization signal has a first pulse width during a first time interval and the controller circuit also includes a half-frame synchronization signal generator which generates a half-frame synchronization signal having a second pulse width, less than the first pulse width, during the first time interval. The controller circuit also includes a data register controller to generate the first and second register control signals as respective pulses during the first time interval. The half-frame synchronization signal is preferably generated as a pulse during a second-half of the first time interval and the first and second register control signals are preferably generated as respective pulses during the second-half of the first time interval. In particular, if the second-half of the first time interval is defined as a second time interval, then the first register control signal is preferably generated as a pulse during a first-half of the second time interval and the second register control signal is preferably generated as a pulse during a second-half of the second time interval.
The preferred serial transfer circuit may also include a transfer register electrically coupled to the serial output port of the shift register. Here, the transfer register is triggered by a first edge of the shift clock signal and the shift register is triggered by a second edge of the shift clock signal. The half-frame synchronization signal generator may also comprise a latch having a data input responsive to the frame synchronization signal and a clock input responsive to the shift clock signal. An AND gate may also be provided having a first input responsive to the half-frame synchronization signal and a second input electrically coupled to an output of the latch. The first and second edges of the shift clock signal may also be established as the rising and falling edges, respectively, and the latch may be triggered by the falling edge of the shift clock signal.
According to another embodiment of the present invention, a preferred method of operating a serial interface circuit includes the steps of generating a half-frame synchronization signal as a first pulse during a first time interval and serially transmitting first data from a plurality of registers within a shift register to an output thereof while simultaneously serially receiving second data into the plurality of registers. Steps are also performed to transfer the second data in parallel from the shift register to a first data register, during a first-half of the first time interval, and then transfer additional first data from a second data register to the plurality of registers within the shift register, during a second-half of the first time interval.